DDR / LPDDR Bandwidth Calculator

Calculate theoretical bandwidth for DDR4, DDR5, LPDDR4, LPDDR5, and LPDDR5X with configurable data rate and bus width.

Live

Input

Memory Type

Data Rate (MT/s)

Bus Width (bits)

Channels

Devices

Use binary units (GiB/s)

Example Configurations

Theoretical Bandwidth

102.40 GB/s

819.2 Gb/s aggregate

Clock Frequency

3200 MHz

6400 MT/s (DDR: 2× clock)

Parameter	Value
Memory type	LPDDR5
Data rate	6400 MT/s
Clock frequency	3200 MHz
Per-channel bus width	32 bits
Total bus width	128 bits
Per-channel bandwidth	25.60 GB/s
Aggregate bandwidth	102.40 GB/s
Aggregate (Gb/s)	819.2 Gb/s

Calculation:

Bandwidth = 6400 MT/s × 128 bits ÷ 8 = 102400 MB/s = 102.40 GB/s

Example input:

LPDDR5 6400 MT/s × 128-bit → 102.4 GB/s

Results

Engineering Notes

MT/s vs GB/s

Data rate in MT/s (mega-transfers per second) is the per-pin transfer rate. To get bytes/s, multiply MT/s × bus width (bits) ÷ 8 bits/byte. For example, LPDDR5 at 6400 MT/s × 128-bit bus = 102400 MB/s = 102.4 GB/s theoretical peak.

DDR5 Channel Architecture

DDR5 introduced two independent 32-bit channels per DIMM (40-bit with ECC). This is different from DDR4 which uses a single 64-bit channel (72-bit with ECC). The dual-channel architecture improves small-granularity access efficiency.

LPDDR Channel Stacking

LPDDR memories often use multiple channels stacked or combined to achieve wider effective bus widths. For example, 4× 32-bit LPDDR5 channels give a 128-bit total bus. Set the channels field to match your system configuration.

Common Mistakes

Using clock frequency instead of data rate

The "data rate" field expects MT/s (mega-transfers per second), not MHz. For DDR, MT/s = 2 × MHz. DDR4-3200 has a 1600 MHz clock but 3200 MT/s data rate.

Counting channels incorrectly for DDR5

DDR5 has 2 independent 32-bit channels per DIMM, not 1×64-bit like DDR4. Make sure to set channels=2 for a single DDR5 DIMM, or adjust for your specific topology.

This tool is intended for engineering analysis and educational purposes. Values and interpretations should be validated against the applicable JEDEC, PCI-SIG, NVM Express, MIPI, vendor datasheet or other authoritative specification.

Frequently Asked Questions

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